A Novel Functional Testing and Verification Technique for Logic Circuits

Functional verification plays a key role in the design verification cycle and the physical fault testing process. There are several functional verification methods that generate tests for modules independent of their implementation ; however, these methods do not scale well for medium to large circuits. In this paper we introduce a new implementation independent functional test generation technique that extracts a good set of functional vectors that are characterized by a small number of neighbors. Two input vectors of a function are considered neighbors if they produce the same output value of the function and the Ham-ming distance between them is one. Our method can be easily implemented and it generates tests by selecting input vectors that have fewer neighbors among all input vectors. Our experimental results demonstrate that our generated tests are significantly better than random tests. Moreover, our method can handle multiple-output circuits, and can be easily scaled to target large designs.